Major Projects

  • Architecture Aware High Level Synthesis
Guide : Asst. Prof. Suhaib A Fahmy
This is my ongoing research project for PhD.
As FPGAs have evolved, with increase in types and capabilities of heterogeneous resources, FPGAs are now being used in wide range of applications. These resources increases the design automation complexity. My work focuses on Embedded DSP Blocks available on Xilinx FPGA Boards. With a wide-range of configuration options possible for DSP Blocks, we have observed that tools provided by Xilinx do not fully utilize these blocks efficiently.
With the aim of providing an end-to-end solution for efficiently implementing mathematical expressions onto DSP Blocks, we have developed a tool, which takes an input expression and generates a synthesisable Verilog RTL code. The tool accepts the input expression from a file, written as 2-input operations, and generates fixed-point Verilog implementations using direct instantiations of DSP Blocks, instead depending on vendor tools. In addition to this, the tool also implements the expression using multiple generic techniques, which could be used by a developer, for the purpose of comparison.
Our results show a significant improvements in maximum frequency achieved (up to 2x), at a minimal cost of additional resources. We are working towards quantifying the error due to truncations at the inputs of DSP blocks for intermediate outputs and more precise implementations, if required.
We have published our work in several prestigious conferences (Publications).

  • Design and Implementation of Architectures for Network Protocols on NetFPGA board
Guide : Dr. Chidamber Kulkarni
I worked on this project as part of Internship at Xilinx Research Labs, INDIA.
The aim of the project was to explore efficient architectures for network protocols using High-Level Synthesis and implement them on NetFPGA board to analyze the performance and shortcomings of the designs.
We implemented the functionality of IP router and Multiprotocol Label Switching (MPLS) in C and explored different architectures for these designs using AutoESL's High-Level Synthesis tool Autopilot.

  • Features based on Fourier-Bessel Expansion for Application of Speaker Identification System
Guide : Prof. R. N. Biswas, Dr. Ram Bilas Pachori
The aim of the project was to develop feature extraction techniques based on Fourier-Bessel (FB) expansion for speaker identification system.
We chose FB expansion because its spectrum representation is better than that of Fourier expansion because each of the Bessel basis functions supports finite bandwidth around a centre frequency and are more analogous to speech signals, unlike the sinusoidal basis functions of Fourier expansion, which provide only spectral lines.
We developed four different feature extraction techniques for speaker identification using zero-order FB functions as basis functions. The Gaussian Mixture Model (GMM) is used for training and identification of speakers. These four developed techniques were implemented on MATLAB and tested on TIMIT database and CHAINS corpus, which are generally used for speaker identification. To check the robustness and reliability of the system, we also tested the techniques on a database of 24 speakers prepared by ourselves at IIIT-Hyderabad. Training and Testing data for the database was recorded in normal office environment.
Click here to see the details of the project.
Click here to download the paper.

  • Pipelined Implementation of JPEG Baseline Image Compression Standard
Guide : Ms. Ipshita Chakrabarty
In this project, we implemented a fully pipelined JPEG baseline image compression standard. The architecture of the design exploits the principles of pipelining and parallelism to obtain high speed and throughput. The design was implemented in Verilog HDL and synthesized for Xilinx Virtex-II Pro FPGA board using Xilinx ISE 10.1.

  • Design and Implementation of a General Purpose Three-stage Pipelined Processor
Guide : Ms. Ipshita Chakrabarty
The aim of the project was to design and implement a processor in Verilog HDL and synthesize it using Synopsys tools. We designed a 32-bit general purpose three-stage pipelined RISC processor with customized instruction set, implemented the same in Verilog HDL and synthesized it using Synopsys Design Tools. Although the circuit was synthesized for a clock frequency of 50 MHz, the gate level processor showed correct results for clock frequency of upto 166.6 MHz (tested in Aldec's Active HDL).
Click here to see the complete architecture of the designed processor.
Click here to see the details of the project.

  • Study of VLSI Multiplication Algorithms
Guide : Prof. M. B. Srinivas
In this project, we studied different types of multipliers and implemented them (at switch level) using HSPICE. We, then, developed low-power unsigned and signed array multipliers based on which an international research paper was accepted in IEEE conference ISCIT-2009. In the proposed multipliers, AND gates are replaced with NOR gates and NAND gates are replaced with OR gates to reduce the power consumption. For signed multiplication, if the numbers are not in two's complement form, the proposed method makes the calculation of two's complement of the numbers redundant, thus reduces time delay also.
Click here to download the paper.

  • Grid Traversal and Mine Detector Robot
Guide : Dr. Madhav Krishna
The objective was to make a robot which could traverse a predefined grid that contained randomly placed mines; and indicate and remember the location of the mines in the grid. The robot was made using basic sensors and its functioning was controlled by a AVR ATMega 8 microcontroller.

  • Barcode Reader
Guide : Prof. Jayanthi Sivaswamy, Prof. Bipin Indurkhya
The aim of the project was to implement a bar code reader which read bar codes of CODE 11 format, using only basic electronics components and some basic ICs (like logic gates, 555 timer, adder, multiplexer, 7-segment decoder etc.). The width of the barcode used was 1mm, the scanner was implemented using three 3mm IR sensors, placed in parallel in such a way that three sensors could simultaneously scan three lines, each 1mm wide.


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