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Ronak Bajaj, Saransh Chhabra, Sreehari Veeramachacheni, M. B. Srinivas, "A Novel, Low-Power Array Multiplier Architecture", in 9th International Symposium on Communication and Information Technology (ISCIT) 2009, September 28-30, Songdo - iFEZ ConvensiA, Icheon, Korea.
Abstract: Low power parallel array multiplier is proposed for both unsigned and two's complement signed multiplication. Modified Baugh-Wooley multiplier is further modified and if input numbers are not in two's complement form, proposed method makes the calculation of two's complement of the number redundant, thus reducing delay. Also power consumption has been found to be less than that of modified Baugh-Wooley multiplier.
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