Publications

Efficient Mapping of Mathematical Expressions into DSP Blocks

Ronak Bajaj, Suhaib A Fahmy, "Efficient Mapping of Mathematical Expressions into DSP Blocks", to be appear in Proceeding of the International Conference on Field Programmable Logic and Applications (FPL), Munich, Germany, Sep 2014.

Abstract: Mapping complex mathematical expressions to DSP blocks through standard inference from pipelined code is inefficient and results in significantly reduced throughput. In this paper, we demonstrate the benefit of considering the structure and pipeline arrangement of DSP blocks during mapping. We have developed a tool that can map mathematical expressions using RTL inference, through high level synthesis with Vivado HLS, and through a custom approach that incorporates DSP block structure. We can show that the proposed method results in circuits that run at around double the frequency of other methods, demonstrating that the structure of the DSP block must be considered when scheduling complex expressions.

Experiments in Mapping Expressions to DSP Blocks

Ronak Bajaj, Suhaib A Fahmy, "Experiments in Mapping Expressions to DSP Blocks", in Proceeding of the International Symposium on Field-Programmable Custom Computing Machines (FCCM), Boston, Massachusetts, May 2014.

Abstract: Mapping complex mathematical expressions to DSP blocks by relying on synthesis from pipelined code is inefficient and results in significantly reduced throughput. We have developed a tool to demonstrate the benefit of considering the structure and pipeline arrangement of the DSP block in mapping of functions. Implementations where the structure of the DSP block is considered during pipelining achieve double the throughput of other methods, demonstrating that the structure of the DSP block must be considered when scheduling complex expressions.

Evaluating the Efficiency of DSP Block Synthesis Inference from Flow Graphs

Ronak Bajaj, Suhaib A Fahmy, "Evaluating the Efficiency of DSP Block Synthesis Inference from Flow Graphs", in Proceeding of the International Conference on Field Programmable Logic and Applications (FPL), Oslo, Norway, Aug 2012.

Abstract: The embedded DSP Blocks in FPGAs have become significantly more capable in recent generations of devices. While vendor synthesis tools can infer the use of these resources, the efficiency of this inference is not guaranteed. Specific language structures are suggested for implementing standard applications but others that do not fit these standard designs can suffer from inefficient synthesis inference. In this paper, we demonstrate this effect by synthesising a number of arithmetic circuits, showing that standard code results in a significant resource and timing overhead compared to considered use of DSP Blocks and their plethora of configuration options through custom instantiation.

Features Based on Fourier-Bessel Expansion for Application of Speaker Identification System

Saransh Chhabra, Ronak Bajaj, R.B. Pachori, R.N. Biswas, "Features Based on Fourier-Bessel Expansion for Application of Speaker Identification System", in Indian Conference for Academic Research by Undergraduate Students (ICARUS) 2010, March 26-28, IIT-Kanpur, Kanpur, INDIA.

Abstract: A compact representation of speech is possible using Bessel functions because of the similarity between voiced speech and the Bessel functions. Both voiced speech and the Bessel functions exhibit quasi-periodicity and decaying amplitude with time. In this paper, we develop various feature extraction techniques using zero-order Bessel functions as basis functions for the task of closed-set text-independent speaker identification. The features are tested on TIMIT, CHAINS and IIIT-Hyderabad speech databases. The performance of the new feature extraction techniques is compared with the results obtained using MFCC features. A generic Gaussian Mixture Model (GMM) classification system is used for speaker modeling. The proposed extraction techniques provide results comparable to the widely used MFCC.

A Novel, Low-Power Array Multiplier Architecture

Ronak Bajaj, Saransh Chhabra, Sreehari Veeramachacheni, M. B. Srinivas, "A Novel, Low-Power Array Multiplier Architecture", in 9th International Symposium on Communication and Information Technology (ISCIT) 2009, September 28-30, Songdo - iFEZ ConvensiA, Icheon, Korea.

Abstract: Low power parallel array multiplier is proposed for both unsigned and two's complement signed multiplication. Modified Baugh-Wooley multiplier is further modified and if input numbers are not in two's complement form, proposed method makes the calculation of two's complement of the number redundant, thus reducing delay. Also power consumption has been found to be less than that of modified Baugh-Wooley multiplier.

Ronak Bajaj