|
|
|
|
|
My objective is to attain a dynamic and challenging platform, which would offer an opportunity to do research where by I can utilize my skills, and further develop the abilities to contribute significantly to the field.
|
|
|
|
|
|
|
|
High Level Synthesis
Reconfigurable Computing
VLSI and Digital Logic Design
|
|
|
|
|
|
Graduation
Bachelor of Technology (Honors) in Electronics and Communication Engnieering (2010)
International Institute of Information Technology, Hyderabad, India
CGPA of 7.65/10.0
|
|
|
|
|
Senior Secondary (2005)
Modi Public School, Kota (Rajasthan), India
Central Board of Secondary Education (CBSE) with 78%
|
|
|
|
|
Secondary (2003)
New Look Central School, Bhilwara (Rajasthan), India
Central Board of Secondary Education (CBSE) with 77.4%
|
|
|
Academic & Extra Curricular Achievements |
|
| Recipient of Research Award at IIIT-H, awarded to undergraduate students for doing recognized research in the respective areas of their specialization.
|
|
| Presented project titled Features based on Fourier-Bessel expansion for application of Speaker Identification system at R&D Showcase 2010 conducted by IIIT-H.
|
|
| Featured in IIIT-H Dean's Merit List for academic excellence.
|
|
| All India Rank 974 out of 525,000(top 0.2%) in All India Engineering Enterance Examination (AIEEE), 2006.
|
|
| Student Placement leader for Graduating batch 2010 at IIIT-H. |
|
| Finance Head, iRC (IIIT-H Robotics Club) in the academic year 2008-09. |
|
| Member of organizing and technical team of Robocamp'08, a National level Robotics workshop help in June 2008 at IIIT-Hyderabad and in August 2008 at KIET, Kakinada, AP (INDIA). |
|
| Organizer of Nexus Hyderabad (an event of IIT-B Techfest 2008), a workshop followed by competition, at IIIT-H. |
|
| Member of technical committee of iRC (IIIT-H Robotics Club). |
|
| Organizer of MnM (Mr and Ms Felicity), one of the major event in IIIT-H's Techno-Cult annual fest FELICITY'07 and FELICITY'08. |
|
| Intern at Xilinx Research Labs, India under Dr. Chidamber Kulkarni. [Sept'2010 - June'2011] |
|
| Worked as Teaching Assistant for Digital Design with HDLs course under the guidance of Ms. Ipshita Chakrabarty during Spring'10 semester at IIIT-H. This was a compulsory course for M.Tech (VLSI) students. Responsibilities included assisting faculty in designing and conducting weekly labs, evaluating assignments and projects, and grading exam scripts. |
|
| Worked as Teaching Assistant for Digital Logic & Processors course under guidance of Prof. P.J. Narayanan (Dean, R&D, IIIT-H) durine Monsoon'09 semester at IIIT-H. Responsibilities included assisting faculty in designing and conducting lab experiments, holding weekly labs and tutorials, and grading assignments and exam scripts. |
|
| Research internship under Prof. M. B. Srinivas at Center for VLSI and Embedded System Technologies (CVEST), IIIT-H during Summer 2008. |
|
| Ronak Bajaj, Suhaib A Fahmy, Evaluating the Efficiency of DSP Block Synthesis Inference from Flow Graphs", to be appear in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), Oslo, Norway, August 2012. |
| Saransh Chhabra, Ronak Bajaj, R B Pachori, R N Biswas, "Features based on Fourier-Bessel Expansion for Application of Speaker Identification System", Indian Conference for Academic Research by Undergraduate Students (ICARUS) 2010, March 26-28, IIT-Kanpur, Kanpur, INDIA. |
| Ronak Bajaj, Saransh Chhabra, Sreehari Veeramachacheni, M. B. Srinivas, "A Novel, Low-Power Array Multiplier Architecture", in 9th International Symposium on Communication and Information Technology (ISCIT) 2009, September 28-30, Songdo - iFEZ ConvensiA, Icheon, Korea. |
|
|
|
|
|
| Operating Systems |
Linux/UNIX, Windows 95/98/ME/XP/Vista |
| Programming Languages |
C, MATLAB, Java (Basic) |
| Hardware Description Language |
Verilog, VHDL |
| Assembly language and Microcontrollers |
INTEL 8085, INTEL 8086, MIPS, NASM, AVR Microcontroller (AtMega8) |
| VLSI tools |
HSPICE, Active-HDL, Multisim, VCS Compiler, Synopsys Design Compiler, MAGIC layout (linux) |
| High-Level Synthesis tools |
AutoESL Autopilot, Synfora PICO(Basic) |
| Web and Scripting Languages |
HTML, XML, Bash |
| Other Tools |
Microsoft Visio 2010, Microsoft Office 2010, Latex, Adobe Photoshop |
|
|
|
|
|
Advanced Digital System Design, Digital Design with HDLs, VLSI Design, Digital Logic Design, |
|
Microprocessor Based System Design, Modern Computer Architecture, Computer Organization, |
|
Computer Programming, Data Structures, Communication Networks, |
|
Electrical Science, Electronics Circuits, Electronics Workshop (I and II), Embedded Robotics, Analog and Digital Circuits, |
|
Design for Testability, Signals and Systems, Digital Signal Processing, |
|
Probability and Random Processes, Analog and Digital Communications, Information Theory and Coding, |
|
Linear Control Systems, Linear Algebra, Numerical Analysis, Electromagnetic Theory |
|
|
|
|
|
|
- Design and Implementation of Architectures for Network Protocols on NetFPGA board
Guide: Dr. Chidamber Kulkarni
I worked on this project as part of Internship at Xilinx Research Labs, INDIA.
The aim of the project was to explore efficient architectures for network protocols using High-Level Synthesis and implement them on NetFPGA board to analyze the performance and shortcomings of the designs.
We implemented the functionality of IP router and Multiprotocol Label Switching (MPLS) in C and explored different architectures for these designs using AutoESL's High-Level Synthesis tool Autopilot.
Tools used: AutoESL Autopilot
|
|
|
|
|
|
|
|
|
|
Features based on Fourier-Bessel Expansion for Application of Speaker Identification System
(B.Tech project)
Guide: Prof. R. N. Biswas, Dr. Ram Bilas pachori
The aim of the project was to develop feature extraction techniques based on Fourier-Bessel (FB) expansion for speaker identification system.
We chose FB expansion because its spectrum representation is better than that of Fourier expansion because each of the Bessel basis functions supports finite bandwidth around a centre frequency and are more analogous to speech signals, unlike the sinusoidal basis functions of Fourier expansion, which provide only spectral lines.
We developed four different feature extraction techniques for speaker identification using zero-order FB functions as basis functions. The Gaussian Mixture Model (GMM) is used for training and identification of speakers. These four developed techniques were implemented on MATLAB and tested on TIMIT database and CHAINS corpus, which are generally used for speaker identification. To check the robustness and reliability of the system, we also tested the techniques on a database of 24 speakers prepared by ourselves at IIIT-Hyderabad. Training and Testing data for the database was recorded in normal office environment.
Tools used: MATLAB
Click here to see the details of the project.
Click here to download the paper.
|
|
|
|
|
|
|
|
|
|
|
Pipelined Implementation of JPEG Baseline Image Compression Standard
Guide: Ms. Ipshita Chakrabarty
In this project, we implemented a fully pipelined JPEG baseline image compression standard. The architecture of the design exploits the principles of pipelining and parallelism to obtain high speed and throughput. The design was implemented in Verilog HDL and synthesized for Xilinx Virtex-II Pro FPGA board using Xilinx ISE 10.1.
Tools used: Xilinx ISE 10.1, XPower Analyzer
|
|
|
|
|
|
|
|
|
|
|
Design and implementation of a general purpose three-staged pipelined processor
Guide: Ms. Ipshita Chakrabarty
The aim of the project was to design and implement a processor in Verilog HDL and synthesize it using Synopsys tools. We designed a 32-bit general purpose three-stage pipelined RISC processor with customized instruction set, implemented the same in Verilog HDL and synthesized it using Synopsys Design Tools. Although the circuit was synthesized for a clock frequency of 50 MHz, the gate level processor showed correct results for clock frequency of upto 166.6 MHz (tested in Aldec's Active HDL).
Tools used: Active-HDL, VCS compiler, Design Vision
Click here to see the complete architecture of designed processor.
Click here to see the details of the project.
|
|
|
|
|
|
|
|
|
|
Study of VLSI Multiplication Algorithms
(Honors Project I)
Guide: Prof. M. B. Srinivas
In this project, we studied different types of multipliers and implemented them (at switch level) using HSPICE. We, then, developed low-power unsigned and signed array multipliers based on which an international research paper was accepted in IEEE conference ISCIT-2009. In the proposed multipliers, AND gates are replaced with NOR gates and NAND gates are replaced with OR gates to reduce the power consumption. For signed multiplication, if the numbers are not in two's complement form, the proposed method makes the calculation of two's complement of the numbers redundant, thus reduces time delay also.
Tools used: HSPICE
Click here to download the paper.
|
|
|
|
|
|
|
|
|
|
Grid Traversal and Mine Detector Robot
(Embedded Robotics course project)
Guide: Dr. Madhav Krishna
The objective was to make a robot which could traverse a predefined grid that contained randomly placed mines; and indicate and remember the location of the mines in the grid. The robot was made using basic sensors and its functioning was controlled by a AVR ATMega 8 microcontroller.
Tools used: AVR studio, Microcontroller programming
|
|
|
|
|
|
|
|
|
|
Barcode Reader
(Electronics Workshop II course project)
Guide: Prof. Bipin Indurkhya, Prof. Jayanthi Sivaswamy
The aim of the project was to implement a bar code reader which read bar codes of CODE 11 format, using only basic electronics components and some basic ICs (like logic gates, 555 timer, adder, multiplexer, 7-segment decoder etc.). The width of the barcode used was 1mm, the scanner was implemented using three 3mm IR sensors, placed in parallel in such a way that three sensors could simultaneously scan three lines, each 1mm wide.
|
|
|
|
|
|
|
|
|
|
Study of Intel Core 2 Extreme Processor (QX6800) Architecture
(Modern Computer Architecture course project)
Guide: Prof. R. Govindarajulu
This project involved a study of the basic architecture of Intel Core 2 Extreme (QX6800) processor highlighting the special features and a comparison with previous designs. [Team size: 2]
|
|
|
|
|
|
|
|
|
|
Natural Disaster System
(Electronics Workshop II course project)
Guide: Prof. Bipin Indurkhya, Prof. Jayanthi Sivaswamy
A working natural disaster control system was built, deployable at regions of high altitude. The main focus was upon the aversion of a flood scenario wherein 3 stages of warning were implemented. It mainly involved the case of handling a long distance communication system. [Team size: 3]
|
|
|
|
|
| I hereby declare that the above mentioned information is true to the best of my knowledge. |
|
|